1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of ultra-shallow, low resistance junctions.
2) Description of the Prior Art
As microelectronic device dimensions decrease, the need to produce ultra-shallow (&lt;60 nm) junctions with low resistance becomes essential. However, conventional ion implantation and annealing processes present several obstacles to formation of ultra-shallow lightly doped source and drain regions necessary for acheiving ultra-shallow junctions with low resistance.
One method of forming ultra-shallow lightly doped source and drain regions is to form a screen oxide layer, implant impurity ions through the screen oxide layer, then perform an anneal to drive in the impurity ions. The disadvantage of this process is that it is susceptible to oxygen enhanced diffusion (OED). OED causes "B" ions to diffuse deeper into the silicon substrate when a screen oxide is used even though the implant depth is shallower than without a screen oxide.
Another process used to form lightly doped source and drain regions is to perform an ion implant and pure N.sub.2 drive in without using a screen oxide. This process does not suffer from OED. However, surface dopant loss occurs during the post implant anneal to drive in the impurity ions. Also, due to reduced gate oxide thicknesses associated with reduced scale devices, the lack of a screen oxide can cause gate oxide integrity degradation due to implantation damage.
An alternate approach is to form a screen oxide, perform impurity ion implantation, strip the screen oxide, then anneal to drive in the impurity ions. Since the screen oxide is removed prior to anneal, this process also suffers from surface dopant loss. Although the screen oxide prevents gate oxide degradation due to implantation damage, oxide stipping can also degrade the gate oxide integrity.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,525,529 (Guldi) discloses a screen oxide or screen oxynitride blocking layer and an NH.sub.3 anneal after ion implantation.
U.S. Pat. No. 5,607,884 (Byun) discloses a NH.sub.3 silicide anneal.
U.S. Pat. No. 5,668,024 (Tsai et al.) discloses a conventional S/D anneal.
U.S. Pat. No. 4,386,968 (Hinkel et al.) shows an ion implantation in O.sub.2.
U.S. Pat. No. 5,296,411 (Gardner et al.) shows a nitridation process to produce reliable oxides.
The following technical literature also provide information on relevant technical developments.
Shishiguchi et al., 33 nm Ultra-Shallow Junction Technology by Oxygen-Free and Point Defect Reduction Process, 1998 Symposium on VLSI Technology Digest of Technology, pp. 134-135 teaches fabrication of ultra-shallow junctions using low-energy ion implantation without a cover-oxide.
Stinson et al., Effects of I/I on Deep Submicron Drain Engineered MOSFET Technologies, IEEE Transactions on Electronic Devices, Vol. 38, No. 3, March 1991, pp. 487-497 examines the effects of ion implantation on gate oxide integrity. While gate oxide degradation is considered insignificant for oxide thicknesses of 7 nm and LDD doses (10E14 cm.sup.2 and lower), the article predicts that gate oxide degradation will increase as scaling down occurs.